Corrected from:
Response of the new version:
When the modulo position is crossing zero, bit 10 in the DI_dnState status is set to TRUE for one cycle.
What happens?
Bit10 in the DI_dnState status does not, as expected, indicate zero crossing in the modulo position.
When does this behaviour occur?
If the modulo traversing range is selected (C2528=2), a FALSE/TRUE edge is expected at DI_dnState bit 10 at every zero crossing of the actual modulo position; the FALSE/TRUE edge is not output.
Which products are affected?
Short-term measures:
As an alternative, use the L_LdZeroDetect to detect zero crossing.
Evaluation/recommendations:
A status bit does not work as expected. The behaviour can be easily detected/diagnosed.
