DFSET, speed-dependent phase trimming C0253, function and default setting

Question:

What is the function of the 'speed-dependent phase trimming' (code C0253) of the digital frequency processing (DFSET) and why is the default value 4000 incr?

Answer:

Because of the cycle times and the arrangement of the function blocks DFSET, DFOUT and DFIN in the processing lists, a delay occurs when the digital frequency (DFSET, DFOUT, DFIN) is generated and transmitted. This delay causes a phase shift,  whose the amount depends on the speed.

The speed-dependent phase trimming can compensate this speed-proportional shift. The phase value of 400 incr. set under C0253 is reached at a speed of 15,000 rpm, see also system manuals 9300, DFSET. The internal positon resolution is 65536 inc/rev. This results in a phase compensation of approx. 250 µs for an assumed fixed delay with default setting.

Calculation of the value to be entered under code C0253 in increments for a set delay in µs:

• C0253 [inc] = delay [µs] * 15000 rpm / 60000 ms/min / 1000 µs/ms * 65536 inc/rev
• C0253 [inc] = delay [µs] * 16,384 inc/µs

Example:
Delay  =  250 µs
C0253 [inc] = 250 µs * 16,384 inc/µs  =  4096 inc

Tip:
See also article on phase synchronisation 20037770